module WB64_ram
#(
    parameter   RAM_SIZE=32*1024
)
(
    input   wire                clk,
    input   wire                rstn,
    input   wire                WB_WEi,
    input   wire                WB_CYCi,
    input   wire    [07:00]     byte_en,
    input   wire    [63:00]     WB_ADRi,
    input   wire    [63:00]     WB_DATi,
    input   wire                WB_STBi,
    output  reg                 WB_ACKo,
    output          [63:00]     WB_DATo
);
localparam RAM_ADDRWID = $clog2(RAM_SIZE) - 3;
genvar i;
wire [RAM_ADDRWID-1:0] addr;
wire ram_access;
wire [63:0]ram_writedata,ram_currdata;

assign addr = WB_ADRi[RAM_ADDRWID + 2 : 3];
assign ram_access =  WB_STBi & WB_CYCi ;

always @( posedge clk ) 
begin
    if( !rstn )         
        WB_ACKo    <= 1'b0;
    else if(ram_access)  
        WB_ACKo    <= 1'b1;
    else            
        WB_ACKo    <= 1'b0;
end
    
generate
    for(i=0;i<8;i=i+1)
    begin
        ram8 #(.RAM_ADDRWID(RAM_ADDRWID)) 
        RAM_BYTE
        (
            .clk(clk),
            .ce(ram_access),
            .addr(addr),
            .di(WB_DATi[i*8+7:i*8]),
            .dato(WB_DATo[i*8+7:i*8]),
            .we(WB_WEi & byte_en[i])
        );

    end
endgenerate

endmodule

module ram8
#(
    parameter RAM_ADDRWID = 10
)
(
    input clk,
    input ce,
    input [RAM_ADDRWID-1:0]addr,
    input [7:0]di,
    output reg[7:0]dato,
    input we
 );
reg [7:0]memcell[2**RAM_ADDRWID-1:0];
always @(posedge clk)
begin
    if(ce)
    begin
        if(we)
            memcell[addr]<=di;
        else
            dato<=memcell[addr];
    end
end

endmodule
